Voltage level conversion circuit

ABSTRACT

A voltage level conversion circuit is provided with a level converter for converting a VDD 1  system input signal into a VDD 2  system signal, and a NOT circuit for inverting the level-converted input signal and outputting the inverted signal, and the outputs of VDD 1  system NOT circuits constituting the level converter are input to only high breakdown voltage transistors in the level converter while a signal having a logical voltage level corresponding to the low power supply voltage VDD 2  is input to low breakdown voltage transistors, and further, only the input signal level-converted by the level converter is input to the NOT circuit.

FIELD OF THE INVENTION

The present invention relates to a voltage level conversion circuit and,more particularly, to a voltage level conversion circuit for convertingan input signal having a logical voltage level corresponding to a firstpower supply voltage into an output signal having a logical voltagelevel corresponding to a second power supply voltage that is lower thanthe first power supply voltage.

BACKGROUND OF THE INVENTION

In recent years, with miniaturization of semiconductor devices, twokinds of voltages, i.e., an external voltage and an internal voltage,are used and the internal voltage is set lower than the externalvoltage. Therefore, there is a request for a circuit for converting thelogical voltage level of a signal between a circuit driven by theexternal voltage and a circuit driven by the internal voltage.

Hereinafter, a description will be given of prior arts with respect to acircuit for converting a logical voltage level corresponding to a highpower supply voltage to a logical voltage level corresponding to a lowpower supply voltage (hereinafter referred to as “voltage levelconversion circuit”).

Generally, as shown in FIG. 6, the conventional voltage level conversioncircuit for converting a logical voltage level corresponding to a highpower supply voltage into a logical voltage level corresponding to a lowpower supply voltage is composed of two stages of NOT circuits.

With reference to FIG. 6, the voltage level conversion circuit 201comprises a front-stage NOT circuit 201 a which is driven by a highpower supply voltage VDD1 and inverts an input signal IN, and arear-stage NOT circuit 201 b which is driven by a low power supplyvoltage VDD2 and inverts an output signal OUT1 of the NOT circuit 201 a.

The front-stage NOT circuit 201 a comprises a P channel MOS transistorQhp11 and an N channel MOS transistor Qhn11 which are connected inseries between the high power supply voltage VDD1 and a ground voltageVSS, and a gate of the power supply side transistor Ohp11 and a gate ofthe ground side transistor Qhn11 are commonly connected. In the NOTcircuit 201 a, a common connection node of the gates is an input node N1a to which the input signal IN is applied, and a connection point of thepower supply side transistor Qhp11 and the ground side transistor Qhn11is an output node N1 b.

The rear-stage NOT circuit 201 b comprises a P channel MOS transistorQhp12 and an N channel MOS transistor Qhn12 which are connected inseries between the low power supply voltage VDD2 and the ground voltageVSS, and a gate of the power supply side transistor Qhp12 and a gate ofthe ground side transistor Qhn12 are commonly connected. In the NOTcircuit 201 b, a common connection node of the gates is an input node N2a to which the output signal OUT1 of the front-stage NOT circuit 201 ais applied, and a connection node of the power supply side transistorQhp12 and the ground side transistor Qhn12 is an output node N2 b.

In the above-mentioned voltage level conversion circuit 201, when theinput signal IN is supplied, the front-stage NOT circuit 201 a invertsthe input signal IN and outputs the signal to the rear-stage NOT circuit201 b. Then, the rear-stage NOT circuit 201 b further inverts theinverted input signal and outputs the signal.

At this time, since the power supply voltage VDD2 of the rear-stage NOTcircuit 201 b is lower than the power supply voltage VDD1 of thefront-stage NOT circuit 201 a, the logical voltage level of the outputsignal OUT of the rear-stage NOT circuit 201 b is lower than the logicalvoltage level of the output signal OUT1 of the front-stage NOT circuit201 a, whereby the logical voltage level of the input signal isconverted from the logical voltage level corresponding to the highvoltage power supply to the logical voltage level corresponding to thelow power supply voltage.

In the voltage level conversion circuit 201 which converts the logicalvoltage level of the input signal using the two stages of NOT circuitsas described above, generally, the respective NOT circuits 201 a and 201b are constituted by VDD1 breakdown voltage transistors having the highpower supply voltage as their breakdown voltages, and the rear-stage NOTcircuit 201 b is driven with the power supply voltage VDD2 which islower than the power supply voltage VDD1 for driving the front-stage NOTcircuit 201 a, and the circuit construction thereof is simple.

In the voltage level conversion circuit 201 comprising the two stages ofNOT circuits, however, since the threshold values of the VDD1 breakdownvoltage transistors constituting the NOT circuits are set at highvalues, it is difficult to operate the rear-stage NOT circuit 201 b witha power supply voltage that is lower than the threshold voltage of theVDD1 breakdown voltage transistor. Although it becomes possible tooperate the rear-stage NOT circuit 201 b with a power supply voltagethat is lower than the threshold voltage of the VDD1 breakdown voltagetransistor by using low-threshold-voltage transistors as the transistorsconstituting the rear-stage NOT circuit 201 b. In this case, however,the breakdown voltage of the transistors constituting the rear-stage NOTcircuit 201 b is lowered, which brings about the possibility of circuitbreakage.

Meanwhile, Japanese Published Patent Application No. Hei. 5-14174(patent literature 1) discloses a level shifter circuit which is able toperform conversion of three values of input and output including highimpedance input and output.

FIG. 7 is a diagram for explaining the level shifter circuit disclosedin the patent literature 1.

The level shifter circuit 202 is a circuit for converting the level ofan input signal applied to an input terminal 1, and outputting thesignal from an output terminal 14.

With reference to FIG. 7, the level shifter circuit 202 comprises afirst resistor 2 and a second resistor 3 which are connected in seriesbetween a power supply voltage VDD1 and a ground voltage VSS; first andsecond inverters 4 and 5 having input nodes connected to a connectionnode n1 of the first and second resistors, respectively; and a levelshifter 6 for converting the level of the output of the first inverter4. The second inverter 5 has a threshold value lower than that of thefirst inverter 4. Further, the level shifter circuit 202 includes a Pchannel MOS transistor 12 and an N channel MOS transistor 13 which areconnected in series between a power supply voltage VDD2 and the groundvoltage VSS, and an output node of the level shifter 6 is connected to agate of the power supply side transistor 12 while an output node of theinverter 5 is connected to a gate of the ground side transistor 13. Aninput terminal 1 of the level shifter circuit 202 is connected to aconnection node n1 of the first resistor 2 and the second resistor 3,and an output terminal 14 thereof is connected to a connection node n2of the transistors 12 and 13.

The level shifter 6 includes an inverter 7 to which an output signal ofthe inverter 4 is applied; a first P channel MOS transistor 8 and afirst N channel MOS transistor 10 which are connected in series betweenthe power supply voltage VDD2 and the ground voltage VSS; and a second Pchannel MOS transistor 9 and a second N channel MOS transistor 11 whichare connected in series between the power supply voltage VDD2 and theground voltage VSS. A connection node n3 of the transistor 8 and thetransistor 10 is connected to a gate of the transistor 9, and aconnection node n4 of the transistor 9 and the transistor 11 isconnected to a gate of the transistor 8. This level shifter 6 converts aVDD1 system signal which is outputted from the inverter 4 and has alogical voltage level corresponding to the high power supply voltageVDD1 into a VDD2 system signal having a logical voltage levelcorresponding to the low power supply voltage VDD2.

Next, the operation of the level shifter circuit 202 will be describedin brief.

In the level shifter circuit 202, when the input voltage applied to theinput terminal 1 is low level, the output voltage of the inverter 4 ishigh level and the output voltage of the inverter 5 is approximatelyhigh level. At this time, the output voltage of the inverter 4 isconverted from the high level logical voltage of the VDD1 system signalinto the high level logical voltage of the VDD2 system signal.Accordingly, the gate voltage VGP of the P channel transistor 12 becomesthe low power supply voltage VDD2 while the gate voltage VGN of the Nchannel transistor 13 becomes the high power supply voltage VDD1,whereby the low level logical voltage (ground voltage) VSS is outputfrom the output terminal 14.

On the other hand, when the voltage applied to the input terminal 1 ishigh level, the output of the inverter 4 is approximately low level andthe output of the inverter 5 is low level. When the output voltage ofthe inverter 4 is approximately low level, the low level logical voltageremains at the ground voltage even when the output voltage of theinverter 4 is converted by the level shifter 6. Accordingly, the gatevoltage VGP of the P channel transistor 12 becomes the ground voltageVSS, and the gate voltage VGN of the N channel transistor 13 becomes theground voltage VSS, whereby the high level logical voltage VDD2 of theVDD2 system signal is output from the output terminal 14.

Further, when the input voltage applied to the input terminal 1 is anintermediate level between the high level and the low level, the outputvoltage of the inverter 4 is high level and the output voltage of theinverter 5 is approximately low level. At this time, the output voltageof the inverter 4 is converted by the level shifter 6 from the highlevel logical voltage of the VDD1 system signal to the high levellogical voltage of the VDD2 system signal. Accordingly, the gate voltageVGP of the P channel transistor 12 becomes the low power supply voltageVDD2 and the gate voltage VGN of the N channel transistor 13 becomes theground voltage VSS. That is, at this time, both of the power supply sidetransistor 12 and the ground side transistor 13 are in the off states,and the output terminal 14 is in the high-impedance state.

This literature has no specific description about the power supplyvoltage VDD1 and the power supply voltage VDD2 of the level shiftercircuit 202. However, like the voltage level conversion circuit 201shown in FIG. 6, when the power supply voltage VDD2 is lower than thepower supply voltage VDD1, the inverter 5 is driven by the high powersupply voltage VDD1, and the high level logical voltage or low levellogical voltage of the VDD1 system signal is applied to the gate of thetransistor 13, and therefore, the transistor 13 needs a modificationsuch as an increase in the thickness of a gate oxide film so as to havethe same breakdown voltage as that of the transistors which constitutethe circuit driven by the high power supply voltage VDD1 (VDD1 systemcircuit). In this case, however, the transistor 13 with the thickness ofthe gate oxide film being increased is included in the circuitsubsequent to the level shifter 6, which is driven by the low powersupply voltage VDD2. Therefore, the low power supply voltage VDD2 cannotbe set at a value that is lower than the threshold value of thetransistor 13, i.e., the threshold value of the transistors of the VDD1system circuit.

Therefore, in contrast to the voltage level conversion circuit shown inFIG. 6, the level shifter circuit 202 disclosed in literature 1 is avoltage level conversion circuit in which the power supply voltage VDD2is higher than the power supply voltage VDD1, i.e., which converts thelogical voltage level corresponding to the low power supply voltage intothe logical voltage level corresponding to the high power supplyvoltage.

As described above, in the conventional voltage level conversion circuit201 comprising the two stages of NOT circuits shown in FIG. 6, since therear-stage NOT circuit having the low power supply voltage VDD2 as apower supply voltage is constituted by the VDD1 breakdown voltage (highbreakdown voltage) system transistors, the threshold voltage of thetransistors is high, and it is difficult to operate the high breakdownvoltage transistors with the low power supply voltage that is lower thanthe threshold voltage. Therefore, the voltage level conversion circuit201 impedes reduction in power consumption by low voltage driving andminiaturization of transistors in the semiconductor device.

Further, as described above, the level shifter circuit 202 shown in FIG.7 is regarded as a circuit for converting a logical voltage levelcorresponding to a low power supply voltage into a logical voltage levelcorresponding to a high power supply voltage. When the circuitconstruction of the level shifter circuit 202 is applied to a voltagelevel conversion circuit for converting a logical voltage levelcorresponding to a high power supply voltage into a logical voltagelevel corresponding to a low power supply voltage, the transistor 13 towhich the logical voltage corresponding to the high power supply voltageis applied comes to have a high breakdown voltage with a thick gateoxide film, and thereby the low power supply voltage cannot be lowerthan the threshold value of the transistor having the high power supplyvoltage as a breakdown voltage.

SUMMARY OF THE INVENTION

The present invention is made to solve the above-described problems andhas for its object to provide a voltage level conversion circuit whichis operable with a lower internal voltage, and converts a logicalvoltage level of an input signal from a logical voltage levelcorresponding to a high power supply voltage into a logical voltagelevel corresponding to a low power supply voltage.

Other objects and advantages of the invention will become apparent fromthe detailed description that follows. The detailed description andspecific embodiments described are provided only for illustration sincevarious additions and modifications within the scope of the inventionwill be apparent to those of skill in the art from the detaileddescription.

According to a first aspect of the present invention, there is provideda voltage level conversion circuit for converting an input signal havinga logical voltage level corresponding to a first power supply voltageinto an output signal having a logical voltage level corresponding to asecond power supply voltage that is lower than the first power supplyvoltage, wherein a first P channel MOS transistor having the secondpower supply voltage as a breakdown voltage and a first N channel MOStransistor having the first power supply voltage as a breakdown voltageare connected in series between the second power supply voltage and aground voltage; a second P channel MOS transistor having the secondpower supply voltage as a breakdown voltage and a second N channel MOStransistor having the first power supply voltage as a breakdown voltageare connected in series between the second power supply voltage and theground voltage; a first connection node of the first P channel MOStransistor and the first N channel MOS transistor is connected to a gateof the second P channel MOS transistor; a second connection node of thesecond P channel MOS transistor and the second N channel MOS transistoris connected to a gate of the first P channel MOS transistor; and theoutput signal is supplied from the second connection node to a circuitthat is driven by the second power supply voltage. In this first aspect,the voltage level conversion circuit for converting the logical voltagelevel of an input signal is provided with a level converter which isdriven by a low power supply voltage and converts the input signalhaving a logical voltage level corresponding to a high power supplyvoltage into an output signal having a logical voltage levelcorresponding to the low power supply voltage, and the output signalwhich is obtained by level-shifting the input signal by the levelconverter is supplied to a circuit driven by the low power supplyvoltage. Therefore, transistors having breakdown voltages equal to thelow power supply voltage can be used as the transistors constituting thecircuit in the rear stage of the level converter. Thereby, it ispossible to set the low power supply voltage of the level converter at avalue lower than the threshold value of the transistor having abreakdown voltage equal to the high power supply voltage, resulting in avoltage level conversion circuit that can be operated by a lowerinternal voltage.

According to a second aspect of the present invention, in the voltagelevel conversion circuit according to the first aspect, the drivingabilities of the first P channel MOS transistor and the second P channelMOS transistor are smaller than the driving abilities of the first Nchannel MOS transistor and the second N channel MOS transistor. In thissecond aspect, since the driving abilities of the first P channelMOS-transistor and the second P channel MOS transistor are set to valuessmaller than the driving abilities of the first N channel MOS transistorand the second N channel MOS transistor, it is possible to speed up theoperation of the level converter when the N channel MOS transistors arein their on states.

According to a third aspect of the present invention, the voltage levelconversion circuit according to the first aspect further includes a NOTcircuit which is constituted by a third P channel MOS transistor havingthe second power supply voltage as a breakdown voltage and a third Nchannel MOS transistor having the second power supply voltage as abreakdown voltage, the driving ability of the third N channel MOStransistor being smaller than the driving ability of the third P channelMOS transistor, and the output signal is supplied through the NOTcircuit to the circuit driven by the second power supply voltage. Inthis third aspect, there is provided the NOT circuit which isconstituted by the third P channel MOS transistor and the third Nchannel MOS transistor having a driving ability lower than that of thethird P channel MOS transistor, and the output signal is suppliedthrough the NOT circuit to the circuit driven by the second power supplyvoltage. Therefore, the NOT circuit in the rear stage of the levelconverter can compensate for the driving ability of the N channel MOStransistor being lower than the driving ability of the P channel MOStransistor in the level converter, whereby the operation speed of thevoltage level conversion circuit as a whole can be further increased.

According to a fourth aspect of the present invention, in the voltagelevel conversion circuit according to the first aspect, a first resistoris inserted between the first P channel MOS transistor and the first Nchannel MOS transistor; and a second resistor is inserted between thesecond P channel MOS transistor and the second N channel MOS transistor.In this fourth aspect, since the resistors are connected in series tothe respective P channel MOS transistors constituting the levelconverter to suppress the driving abilities of transistors, the drivingefficiencies of the N channel transistors constituting the levelconverter are substantially enhanced, whereby the operation of the levelconverter can be speeded up when the N channel MOS transistors are intheir on states.

According to a fifth aspect of the present invention, the voltage levelconversion circuit according to the first aspect comprises a fifth Pchannel MOS transistor connected between the first connection node andthe second power supply voltage; a sixth P channel MOS transistorconnected between the second connection node and the second power supplyvoltage; a first signal generation circuit for applying a one-shot pulsevoltage for turning on the sixth P channel MOS transistor to a gate ofthe sixth P channel MOS transistor, when an L level logical voltagegenerated at the first connection node is detected; and a second signalgeneration circuit for applying a one-shot pulse voltage for turning onthe fifth P channel MOS transistor to a gate of the fifth P channel MOStransistor, when an L level logical voltage generated at the secondconnection node is detected. In this fifth aspect, since there areprovided the auxiliary P channel MOS transistors for supporting theoperations of the P channel MOS transistors in the level converter andthe auxiliary P channel MOS transistors are driven by the one-shotpulses, respectively, the voltage level conversion circuit can beoperated at higher speed with more stability.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram for explaining a voltage level conversion circuitaccording to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a voltage level conversion circuitaccording to a second embodiment of the present invention.

FIG. 3 is a diagram for explaining a voltage level conversion circuitaccording to a third embodiment of the present invention.

FIG. 4 is a diagram for explaining a voltage level conversion circuitaccording to a fourth embodiment of the present invention.

FIG. 5 is a diagram for explaining a voltage level conversion circuitaccording to a fifth embodiment of the present invention.

FIG. 6 is a diagram for explaining the conventional voltage levelconversion circuit.

FIG. 7 is a diagram for explaining the level shift circuit described inliterature 1.

PREFERRED EMBODIMENTS OF THE PRESENT INVENTION

Hereinafter, preferred embodiments of the present invention will bedescribed.

Embodiment 1

FIG. 1 is a circuit diagram for explaining a voltage level conversioncircuit 101 according to a first embodiment of the present invention.

The voltage level conversion circuit 101 according to the firstembodiment is a circuit for converting an input signal having a logicalvoltage level of a high power supply voltage system (VDD1 system) intoan output signal having a logical voltage level of a low power supplyvoltage system (VDD2 system). The voltage level conversion circuit 101includes a level converter which comprises a high breakdown voltage Nchannel MOS transistor and a low breakdown voltage P channel MOStransistor having a threshold value lower than that of the N channel MOStransistor, wherein the VDD1 system input signal is input to only thegate of the high breakdown voltage N channel MOS transistor, and thelevel converter outputs the input signal that is level-converted by thelevel converter to a circuit that is driven by the low power supplyvoltage, whereby the VDD2 system power supply voltage is reduced.

With reference to FIG. 1, the voltage level conversion circuit 101includes a level converter 101 a for converting the VDD1 system inputsignal into the VDD2 system signal; and a NOT circuit 30 for invertingthe level-converted input signal and outputting the inverted signal.Reference numeral 21 a denotes a first NOT circuit for inverting aninput signal IN, and numeral 21 b denotes a second NOT circuit forinverting the output signal of the first NOT circuit 21 a. Further, afirst P channel MOS transistor Qlp1 having the low power supply voltageVDD2 as a breakdown voltage and a first N channel MOS transistor Qhn1having the high power supply voltage VDD1 as a breakdown voltage areconnected in series between the low power supply voltage VDD2 as thesecond power supply voltage and the ground voltage VSS, and a second Pchannel MOS transistor Qlp2 having the low power supply voltage VDD2 asa breakdown voltage and a second N channel MOS transistor Qhn2 havingthe high power supply voltage VDD1 as a breakdown voltage are connectedin series between the low power supply voltage VDD2 as the second powersupply voltage and the ground voltage VSS. A connection node N11 of theP channel MOS transistor Qlp1 and the N channel MOS transistor Qhn1 isconnected to the gate of the P channel MOS transistor Qlp2, and aconnection node N12 of the P channel MOS transistor Qlp2 and the Nchannel MOS transistor Qhn2 is connected to the gate of the P channelMOS transistor Qlp1. A node N13 is an output node of the NOT circuit 21a, and it is connected to the gate of the N channel MOS transistor Qhn1and to an input node of the NOT circuit 21 b. Further, a node N14 is anoutput node of the NOT circuit 21 b, and it is connected to the gate ofthe N channel MOS transistor Qhn2.

The voltage level conversion circuit 101 converts the level of the inputsignal IN inputted to the input node of the NOT circuit 21 a, andoutputs the level-converted input signal to the circuit driven by thelow power supply voltage VDD2 through the connection node N12 of the Pchannel MOS transistor Qlp2 and the N channel MOS transistor Qhn2.

The first P channel MOS transistor Qlp1, the second P channel MOStransistor Qlp2, and the MOS transistor constituting the NOT circuit 30are low breakdown voltage transistors having a low threshold value, andthese transistors belong to the circuit system A2 driven by the lowpower supply voltage VDD2 (VDD2 system). On the other hand, the first Nchannel MOS transistor Qhn1, the second N channel MOS transistor Qhn2,and the MOS transistors (not shown) constituting the inverters 21 a and21 b are high breakdown voltage transistors having a high thresholdvalue, and these transistors belong to the circuit system Al driven bythe high power supply voltage VDD1 (VDD1 system).

Next, the operation will be described.

When the VDD1 system input signal IN is input to the voltage levelconversion circuit 101, the input signal IN is inverted by the NOTcircuit 21 a, and a NOT signal of the input signal IN is input to thegate of the first N channel MOS transistor Qhn1 and to the NOT circuit21 b. The NOT signal of the input signal IN is inverted by the NOTcircuit 21 b and inputted to the gate of the second N channel MOStransistor Qhn2.

For example, when the voltage of the input signal IN is an L levellogical voltage (=VSS), the gate voltage of the first N channeltransistor Qhn1 becomes the H level logical voltage (=VDD1) while thegate voltage of the second N channel transistor Qhn2 becomes the L levellogical voltage (=VSS), and the N channel transistor Qhn1 is turned onwhile the N channel transistor Qhn2 is turned off. Then, the voltage atthe first connection node N11 becomes the L level logical voltage(=VSS), whereby the second P channel MOS transistor Qlp2 is turned on,and the voltage at the second connection node N12 becomes the H levellogical voltage (=VDD2). Since the voltage at the second connection nodeN12 becomes the gate voltage of the first P channel MOS transistor Qlp1,the transistor Qlp1 is in the off state, and the voltage at the firstconnection node N11 is decided at the L level logical voltage (=VSS).

On the other hand, when the voltage of the input signal IN is the Hlevel logical voltage (=VDD1), the first P channel transistor Qlp1 andthe second N channel transistor Qhn2 are turned on while the second Pchannel transistor Qhp2 and the first N channel transistor Qhn1 areturned off, whereby the voltage at the first connection node N11 becomesthe H level logical voltage (=VDD2) while the voltage at the secondconnection node N12 becomes the L level logical voltage (=VSS).

Then, the logical voltage of the second connection node N12 is invertedby the NOT circuit 30 that is driven by the low power supply voltageVDD2, and the inverted output of the NOT circuit 30 is output to theVDD2 system circuit as an output signal OUT of the voltage levelconversion circuit 101.

As described above, in the voltage level conversion circuit 101according to the first embodiment, the outputs of the VDD1 system NOTcircuits 21 a and 21 b are input to only the high breakdown voltagetransistors Qhn1 and Qhn2 while the signal having the logical voltagelevel corresponding to the low power supply voltage VDD2 is input to thelow breakdown voltage transistors Qlp1 and Qlp2 having the low powersupply voltage VDD2 as a power supply voltage, and low breakdown voltagetransistors having a low threshold value are used as the transistorsQlp1 and Qlp2 having the low power supply voltage as a power supplyvoltage, and further, only the input signal that is level-converted bythe level converter 101 a is input to the rear-stage NOT circuit 30 ofthe level converter 101 a. Therefore, a low breakdown voltage transistorhaving a low threshold value can be used as a transistor constitutingthe NOT circuit 30. Thereby, the low power supply voltage VDD2 as theVDD2 system power supply voltage can be made lower than the thresholdvalue of the VDD1 system high breakdown voltage transistor, resulting infurther reduction in the low power supply voltage VDD2.

Furthermore, in the above-mentioned first embodiment, by setting thedriving abilities of the first and second P channel MOS transistors Qlp1and Qlp2 at values smaller than the driving abilities of the first andsecond N channel MOS transistors Qhn1 and Qhn2, respectively, the amountof charges that flow into the connection node N11 or N12 from the Pchannel MOS transistor Qlp1 or Qlp2 can be reduced when the N channelMOS transistor Qhn1 or Qhn2 is turned on and electric charges are drawnfrom the connection node N11 or N12 by the N channel MOS transistor Qhn1or Qhn2, whereby the voltage level conversion circuit can be operated athigher speed when the N channel MOS transistors Qhn1 and Qhn2 are intheir on states.

Embodiment 2

FIG. 2 is a circuit diagram for explaining a voltage level conversioncircuit according to a second embodiment of the present invention.

A voltage level conversion circuit 102 according to the secondembodiment is provided with, instead of the NOT circuit 30 of thevoltage level conversion circuit according to the first embodiment, aNOT circuit 31 for adjusting the balance of transistor performance in alevel converter 101 a, and an output signal from the NOT circuit 31 isoutput through an output circuit 41 for waveform shaping.

In FIG. 2, the voltage level conversion circuit 102 includes a levelconverter 101 a of the same construction as that according to the firstembodiment, a NOT circuit 31 for inverting a signal outputted from thelevel converter 101 a, and an output circuit 41 for shaping the waveformof a NOT signal outputted from the NOT circuit 31 and outputting thesignal. The NOT circuit 31 comprises a third P channel MOS transistorQlp7 and a third N channel MOS transistor Qln7 which are connected inseries between the high-low power supply voltage VDD2 and the groundvoltage VSS, and the gate of the power supply side transistor Qlp7 andthe gate of the ground side transistor Qln7 are commonly connected to asecond connection node N12 of the level converter 101 a. As for theratio of the driving abilities of the third P channel MOS transistorQlp7 and the third N channel MOS transistor Qln7, the driving ability ofthe P channel MOS transistor is larger than the driving ability of the Nchannel MOS transistor so that the level of the output signal OUTchanges at high speed when the voltage at the connection node N12changes from an H level logical voltage to a L level logical voltage.

Further, the output circuit 41 has, as an input node, a connection nodeN15 of the two MOS transistors Qlp7 and Qln7 which are connected inseries and constitute the NOT circuit 31, and comprises two stages ofNOT circuits 41 a and 41 b.

The transistors Qlp7 and Qln7 constituting the NOT circuit 31 and thetransistors (not shown) constituting the two stages of NOT circuits 41 aand 41 b of the output circuit 41 are low breakdown voltage transistorshaving a low threshold value, and these transistors belong to a VDD2system A2 which is driven by the low power supply voltage VDD2, as wellas the first P channel MOS transistor Qlp1 and the second P channel MOStransistor Qlp2.

Next, the operation will be described.

The operation of the level converter 101 a of the voltage levelconversion circuit 102 according to the second embodiment is identicalto that of the first embodiment, and the input signal IN that islevel-converted by the level converter 101 a is output to the NOTcircuit 31 from the second connection node N12 of the level converter101 a.

In the NOT circuit 31, since the driving ability of the power supplyside P channel MOS transistor Qlp7 is larger than the driving ability ofthe ground side N channel MOS transistor Qln7, when the voltage at theconnection node N12 changes from the H level logical voltage to the Llevel logical voltage, the voltage at the output node N15 changes athigh speed.

That is, since a VDD1 system high breakdown voltage transistor is usedfor the N channel MOS transistor Qhn2, the driving ability of thistransistor Qhn2 is generally low, and therefore, the operation ofchanging the voltage level at the connection node N12 from the H levelto the L level is slow. In this second embodiment, reduction in theoperation speed of the whole voltage level conversion circuit due to thelow driving ability of the VDD1 system transistor can be offset byincreasing the driving ability of the P channel MOS transistor Qln7constituting the next-stage NOT circuit of the level converter 101 a,resulting in high-speed operation of the voltage level conversioncircuit.

As described above, in the voltage level conversion circuit 102according to the second embodiment, as in the first embodiment, the VDD1system signal having the logical voltage level corresponding to the highpower supply voltage VDD1 is input to only the high breakdown voltagetransistors Qhn1 and Qhn2 while the VDD2 system signal having thelogical voltage level corresponding to the low power supply voltage VDD2is input to the low breakdown voltage transistors Qlp1 and Qlp2, and lowbreakdown voltage transistors having a low threshold value are used asthe transistors Qlp1 and Qlp2 having the low power supply voltage VDD2as a power supply voltage, and further, only the VDD2 system signal thatis level-converted by the level converter 101 a is input to therear-stage NOT circuit 31 of the level converter 101 a, and therefore, alow breakdown voltage transistor having a low threshold value can beused as the transistor constituting the NOT circuit 31. Thereby, the lowpower supply voltage VDD2 as the VDD2 system power supply voltage can bemade lower than the threshold value of the VDD1 system high breakdownvoltage transistor, resulting in further reduction in the low powersupply voltage VDD2.

Further, the driving ability of the power supply side P channel MOStransistor is set to a larger value between the P channel MOS transistorand the N channel MOS transistor constituting the NOT circuit 31.Therefore, the low driving ability and the low-speed operation of theVDD1 system N channel MOS transistor Qhn2 in the level converter 101 acan be compensated by the rear-stage NOT circuit 31 of the levelconverter 101 a, resulting in high-speed operation of the whole voltagelevel conversion circuit.

Embodiment 3

FIG. 3 is a circuit diagram for explaining a voltage level conversioncircuit according to a third embodiment of the present invention.

A voltage level conversion circuit 103 according to the third embodimentis provided with a level converter 103 a instead of the level converter101 a of the voltage level conversion circuit according to the firstembodiment.

The level converter 103 a of the voltage level conversion circuitaccording to the third embodiment is constructed by inserting a resistorR1 between the first connection node N11 and the first P channel MOStransistor Qlp1 in the level converter 101 a according to the firstembodiment, and inserting a resistor R2 between the second connectionnode N12 and the second P channel MOS transistor Qlp2 in the levelconverter 101 a.

The resistor R1 comprises a P channel MOS transistor Qlp3 which isconnected in series between the first connection node N11 and the firstP channel MOS transistor Qlp1, and has a gate connected to the groundvoltage VSS. Further, the resistor R2 comprises a P channel MOStransistor Qlp4 which is connected in series between the secondconnection node N12 and the second P channel MOS transistor Qlp2, andhas a gate connected to the ground voltage VSS.

Next, the operation will be described.

The fundamental operation of the voltage level conversion circuit 103according to the third embodiment is identical to that of the firstembodiment.

In this third embodiment, however, since the resistor R1 is insertedbetween the first connection node N11 and the first P channel MOStransistor Qlp1 and the resistor R2 is inserted between the secondconnection node N12 and the second P channel MOS transistor Qlp2, theabilities of the P channel MOS transistors to drive the connection nodesN11 and N12 are suppressed. Therefore, the effects of driving theconnection nodes N11 and N12 by the N channel MOS transistors Qhn1 andQhn2 are substantially improved.

As described above, according to the third embodiment, as in the firstembodiment, the VDD1 system signal having the logical voltage levelcorresponding to the high power supply voltage VDD1 is input to only thehigh breakdown voltage transistors Qhn1 and Qhn2 while the VDD2 systemsignal having the logical voltage level corresponding to the low powersupply voltage VDD2 is input to the low breakdown voltage transistorsQlp1 and Qlp2 and the NOT circuit 30, and therefore, low breakdownvoltage transistors having a low threshold value can be used as the VDD2system transistors Qlp1 and Qlp2 constituting the level converter 1O3 aand the transistor constituting the NOT circuit 30. Thereby, the lowpower supply voltage VDD2 as the VDD2 system power supply voltage can bemade lower than the threshold value of the VDD1 system high breakdownvoltage transistor, resulting in further reduction in the low powersupply voltage VDD2.

Further, since the resistors are connected in series to the power supplyside P channel transistors Qlp1 and Qlp2 constituting the levelconverter 103 a to suppress the driving abilities of these transistors,the driving efficiencies of the ground side N channel transistors Qhn1and Qhn2 are substantially increased, whereby the ground voltage levelof the signal outputted from the NOT circuit 30 can be speedily decided.

Embodiment 4

FIG. 4 is a circuit diagram for explaining a voltage level conversioncircuit according to a fourth embodiment of the present invention.

A voltage level conversion circuit 104 according to the fourthembodiment is provided with a circuit structure for supporting theoperation of the power supply side transistors Qlp1 and Qlp2 of thelevel converter 101 a, in addition to the voltage level conversioncircuit 101 according to the first embodiment.

With reference to FIG. 4, the voltage level conversion circuit 104includes a level converter 101 a for converting an input signal having alogical voltage level of a high power supply voltage system (VDD1system) into an output signal having a logical voltage level of a lowpower supply voltage system (VDD2 system) and outputting thelevel-converted signal, and a NOT circuit 30 for inverting thelevel-converted signal and outputting the inverted signal.

Further, the voltage level conversion circuit 104 includes a fifth Pchannel MOS transistor Qlp5 which is connected in parallel to the powersupply side P channel MOS transistor Qlp1 of the level converter 101 aand supports the operation of the transistor Qlp1 to charge theconnection node N11, a sixth P channel MOS transistor Qlp6 which isconnected in parallel to the power supply side P channel MOS transistorQlp2 of the level converter 101 a and supports the operation of thetransistor Qlp2 to charge the connection node N12, and first and secondpulse signal generation circuits P1 and P2 for driving these auxiliarytransistors Qlp5 and Qlp6 with pulse signals, respectively.

The pulse signal generation circuit P1 for driving the transistor Qlp6comprises four stages of NOT circuits Pla to Pld for successivelyinverting the voltage level of the connection node N11 of the levelconverter 101 a, and a two-input NAND circuit Ple to which the output ofthe first-stage NOT circuit Pla and the output of the fourth-stage NOTcircuit Pld are input, respectively, wherein an output node N16 of thetwo-input NAND circuit Ple is connected to the gate of the P channel MOStransistor Qlp6.

Furthermore, the pulse signal generation circuit P2 for driving thetransistor Qlp5 comprises four stages of NOT circuits P2 a to P2 d forsuccessively inverting the voltage level of the connection node N12 ofthe level converter 101 a, and a two-input NAND circuit P2 e to whichthe output of the first-stage NOT circuit P2 a and the output of thefourth-stage NOT circuit P2 d are input, respectively, wherein an outputnode N15 of the two-input NAND circuit P2 e is connected to the gate ofthe P channel MOS transistor Qlp5.

The auxiliary transistors Qlp5 and Qlp6 and the transistors constitutingthe pulse signal generation circuits P1 and P2 are low breakdown voltagetransistors having a low threshold value, and these transistors belongto a circuit system (VDD2 system) driven by the low power supply voltageVDD2.

Next, the operation will be described.

When a VDD1 system input signal IN is input to the voltage levelconversion circuit 104, the input signal IN is inverted by the NOTcircuit 21 a, and a NOT signal of the input signal IN is input to thegate of the first N channel MOS transistor Qhn1 and to the NOT circuit21 b. The NOT signal of the input signal IN is inverted by the NOTcircuit 21 b and input to the gate of the second N channel MOStransistor Qhn2.

For example, when the voltage of the input signal IN is the L levellogical voltage (=VSS), the gate voltage of the first N channeltransistor Qhn1 is the H level logical voltage (=VDD1) while the gatevoltage of the second N channel transistor Qhn2 is the L level logicalvoltage (=VSS), and the N channel transistor Qhn1 is turned on while theN channel transistor Qhn2 is turned off.

Then, the voltage of the first connection node N11 becomes the L levellogical voltage (=VSS), and the second P channel MOS transistor Qlp2 isturned on and starts charging of the second connection node N12. At thistime, the voltage of the first connection node N11 is input to the firstpulse generation circuit P1, and a one shot pulse signal outputted fromthe pulse generation circuit P1 and having a pulse width according tothe number of the stages of the NOT circuits Pla to Pld is applied tothe gate of the P channel MOS transistor Qlp6, whereby the transistorQlp6 starts charging of the second connection node N12. Thereby, theoperation of the second P channel MOS transistor Qlp2 is supported bythe P channel MOS transistor Qlp6.

Furthermore, since the voltage of the second connection node N12 is thegate voltage of the first P channel MOS transistor Qlp1, the transistorQlp1 is in the off state, and the voltage of the first connection nodeN11 is decided at the L level logical voltage (=VSS).

On the other hand, when the voltage of the input signal IN is the Hlevel logical voltage (=VDD1), the gate voltage of the first N channeltransistor Qhn1 becomes the L level logical voltage (=VSS) while thegate voltage of the second N channel transistor Qhn2 is the H levellogical voltage (=VDD1), and thereby the N channel transistor Qhn1 isturned off while the N channel transistor Qhn2 is turned on.

Then, the voltage of the second connection node N12 becomes the L levellogical voltage (=VSS), whereby the first P channel MOS transistor Qlp1is turned on and starts charging of the first connection node N11. Atthis time, the voltage of the second connection node N12 is input to thesecond pulse signal generation circuit P2, and a one shot pulse signaloutputted from the pulse generation circuit P2 and having a pulse widthaccording to the number of the stages of the NOT circuits P2 a to P2 dis applied to the gate of the P channel MOS transistor Qlp5, whereby thetransistor Qlp5 starts charging of the first connection node N11.Thereby, the operation of the first P channel MOS transistor Qlp1 issupported by the P channel MOS transistor Qlp5.

Furthermore, since the voltage of the first connection node N11 is thegate voltage of the second P channel MOS transistor Qlp2, the transistorQlp2 is in the off state, and the voltage of the second connection nodeN12 is decided at the L level logical voltage (=VSS).

Then, the logical voltage of the second connection node N12 is invertedby the NOT circuit 30 that is driven by the low power supply voltageVDD2, and the inverted output from the NOT circuit 30 is output to theVDD2 system circuit as an output signal OUT of the voltage levelconversion circuit 104.

As described above, according to the fourth embodiment, as in the firstembodiment, the VDD1 system signal having the logical voltage levelcorresponding to the high power supply voltage VDD1 is input to only thehigh breakdown voltage transistors Qhn1 and Qhn2, and the VDD2 systemsignal having the logical voltage level corresponding to the low powersupply voltage VDD2 is input to the low breakdown voltage transistorsQlp1 and Qlp2 and the NOT circuit 30. Therefore, low breakdown voltagetransistors having a low threshold value can be used as the VDD2 systemtransistors Qlp1 and Qlp2 constituting the level converter 101 a and thetransistor constituting the NOT circuit 30, whereby the low power supplyvoltage VDD2 as the VDD2 system power supply voltage can be made lowerthan the threshold value of the VDD1 system high breakdown voltagetransistor, resulting in further reduction in the low power supplyvoltage VDD2.

Further, the voltage level conversion circuit according to the fourthembodiment is provided with the P channel transistor Qlp5 that supportsthe operation of the power supply side P channel transistor Qlp1 of thelevel converter 101 a to charge the connection node N11, and the Pchannel transistor Qlp6 that supports the operation of the power supplyside P channel transistor Qlp2 of the level converter 101 a to chargethe connection node N12, and these auxiliary transistors Qlp5 and Qlp6are driven by one-shot pulse signals outputted from the pulse signalgeneration circuits P1 and P2, resulting in a voltage level conversioncircuit capable of more stable high-speed operation as compared with thefirst embodiment.

Embodiment 5

FIG. 5 is a circuit diagram for explaining a voltage level conversioncircuit according to a fifth embodiment of the present invention.

A voltage level conversion circuit 105 according to the fifth embodimentis provided with a level converter 105 a of the same construction as thelevel converter 103 a of the third embodiment, instead of the levelconverter 101 a of the voltage level conversion circuit according to thefourth embodiment. In other words, the voltage level conversion circuit105 of this fifth embodiment has a circuit structure obtained bycombining the third embodiment and the fourth embodiment.

In the level converter 105 a of the voltage level conversion circuitaccording to the fifth embodiment, a resistor R1 is inserted between thefirst connection node N11 and the first P channel MOS transistor Qlp1 inthe level converter 101 a according to the fourth embodiment, and aresistor R2 is inserted between the second connection node N12 and thesecond P channel MOS transistor Qlp2 in the level converter 101 a.

The resistor R1 comprises a P channel MOS transistor Qlp3 which isconnected in series between the first connection node N11 and the firstP channel MOS transistor Qlp1, and has a gate connected to the groundvoltage VSS. Further, the resistor R2 comprises a P channel MOStransistor Qlp4 which is connected in series between the secondconnection node N12 and the second P channel MOS transistor Qlp2, andhas a gate connected to the ground voltage VSS.

Next, the operation will be described.

The fundamental operation of the voltage level conversion circuit 105according to the fifth embodiment is identical to that of the fourthembodiment.

In this fifth embodiment, however, since the resistor R1 is insertedbetween the first connection node N11 and the first P channel MOStransistor Qlp1 and the resistor R2 is inserted between the secondconnection node N12 and the second P channel MOS transistor Qlp2, theabilities of the P channel MOS transistors to drive the connection nodesN11 and N12 are suppressed, and thereby the effects of driving theconnection nodes N11 and N12 by the N channel MOS transistors Qhn1 andQhn2 are substantially improved.

As described above, according to the fifth embodiment, as in the firstembodiment, the VDD1 system signal having the logical voltage levelcorresponding to the high power supply voltage VDD1 is input to only thehigh breakdown voltage transistors Qhn1 and Qhn2 while the VDD2 systemsignal having the logical voltage level corresponding to the low powersupply voltage VDD2 is input to the low breakdown voltage transistorsQlp1 and Qlp2 and the NOT circuit 30, and therefore, low breakdownvoltage transistors having a low threshold value can be used as the VDD2system transistors Qlp1 and Qlp2 constituting the level converter 1O5 aand the transistor constituting the NOT circuit 30. Thereby, the lowpower supply voltage VDD2 as the VDD2 system power supply voltage can bemade lower than the threshold value of the VDD1 system high breakdownvoltage transistor, resulting in further reduction in the low powersupply voltage VDD2.

Further, in this fifth embodiment, as in the third embodiment, since theresistors are connected in series to the power supply side P channeltransistors Qlp1 and Qlp2 constituting the level converter 105 a tosuppress the driving abilities of these transistors, the drivingefficiencies of the ground side N channel transistors Qhn1 and Qhn2 aresubstantially improved, whereby the ground voltage level of the signaloutputted from the NOT circuit 30 can be speedily decided.

Further, in this fifth embodiment, as in the fourth embodiment, the Pchannel transistor Qlp5 supports the operation of the power supply sideP channel transistor Qlp1 of the level converter 105 a to charge theconnection node N11, and the P channel transistor Qlp6 supports theoperation of the power supply side P channel transistor Qlp2 of thelevel converter 105 a to charge the connection node N12, resulting in avoltage level conversion circuit capable of more stable high-speedoperation as compared with the first embodiment.

APPLICABILITY IN INDUSTRY

A voltage level conversion circuit according to the present inventionrealizes an operation with a lower internal voltage in a circuit forconverting a logical voltage level from a logical voltage levelcorresponding to a high power supply voltage to a logical voltage levelcorresponding to a low power supply voltage, and it is useful inreducing the low power supply voltage that drives the voltage levelconversion circuit.

1. A voltage level conversion circuit for converting an input signalhaving a logical voltage level corresponding to a first power supplyvoltage into an output signal having a logical voltage levelcorresponding to a second power supply voltage that is lower than thefirst power supply voltage, said voltage level conversion circuit beingfor use with a circuit that is to be driven by the second power supplyvoltage, said voltage level conversion circuit comprising: a first Pchannel MOS transistor, having the second power supply voltage as abreakdown voltage, and a first N channel MOS transistor, having thefirst power supply voltage as a breakdown voltage, connected in seriesbetween the second power supply voltage and a ground voltage; a second Pchannel MOS transistor, having the second power supply voltage as abreakdown voltage, and a second N channel MOS transistor having thefirst power supply voltage as a breakdown voltage, connected in seriesbetween the second power supply voltage and the ground voltage; a firstconnection node, between the first P channel MOS transistor and thefirst N channel MOS transistor, connected to a gate of the second Pchannel MOS transistor; and a second connection node, between the secondP channel MOS transistor and the second N channel MOS transistor,connected to a gate of the first P channel MOS transistor; wherein saidoutput signal is to be supplied via the second connection node to thecircuit that is to be driven by the second power supply voltage; thedriving abilities of the first P channel MOS transistor and the second Pchannel MOS transistor are smaller than the driving abilities of thefirst N channel MOS transistor and the second N channel MOS transistor;and the voltage level conversion circuit further comprising: a firstresistor connected between the first P channel MOS transistor and thefirst connection node; and a second resistor connected between thesecond P channel MOS transistor and the second connection node.
 2. Avoltage level conversion circuit for converting an input signal having alogical voltage level corresponding to a first power supply voltage intoan output signal having a logical voltage level corresponding to asecond power supply voltage that is lower than the first power supplyvoltage, said voltage level conversion circuit being for use with acircuit that is to be driven by the second power supply voltage, saidvoltage level conversion circuit comprising: a first P channel MOStransistor, having the second power supply voltage as a breakdownvoltage, and a first N channel MOS transistor, having the first powersupply voltage as a breakdown voltage, connected in series between thesecond power supply voltage and a ground voltage; a second P channel MOStransistor, having the second power supply voltage as a breakdownvoltage, and a second N channel MOS transistor having the first powersupply voltage as a breakdown voltage, connected in series between thesecond power supply voltage and the ground voltage; a first connectionnode, between the first P channel MOS transistor and the first N channelMOS transistor, connected to a gate of the second P channel MOStransistor; a second connection node, between the second P channel MOStransistor and the second N channel MOS transistor, connected to a gateof the first P channel MOS transistor; a fifth P channel MOS transistorconnected between the first connection node and the second power supplyvoltage; a sixth P channel MOS transistor connected between the secondconnection node and the second power supply voltage; a first signalgeneration circuit for applying a one-shot pulse voltage for turning onthe sixth P channel MOS transistor to a gate of the sixth P channel MOStransistor, when an L level logical voltage generated at the firstconnection node is detected; and a second signal generation circuit forapplying a one-shot pulse voltage for turning on the fifth P channel MOStransistor to a gate of the fifth P channel MOS transistor, when an Llevel logical voltage generated at the second connection node isdetected; wherein said output signal is to be supplied via the secondconnection node to the circuit that is to be driven by the second powersupply voltage.
 3. A voltage level conversion circuit as defined inclaim 2 further comprising: a first resistor connected between the firstP channel MOS transistor and the first connection node; and a secondresistor connected between the second P channel MOS transistor and thesecond connection node.
 4. A voltage level conversion circuit forconverting an input signal having a logical voltage level correspondingto a first power supply voltage into an output signal having a logicalvoltage level corresponding to a second power supply voltage that islower than the first power supply voltage, said voltage level conversioncircuit being for use with a circuit that is to be driven by the secondpower supply voltage, said voltage level conversion circuit comprising:a first P channel MOS transistor, having the second power supply voltageas a breakdown voltage, and a first N channel MOS transistor, having thefirst power supply voltage as a breakdown voltage, connected in seriesbetween the second power supply voltage and a ground voltage; a second Pchannel MOS transistor, having the second power supply voltage as abreakdown voltage, and a second N channel MOS transistor having thefirst power supply voltage as a breakdown voltage, connected in seriesbetween the second power supply voltage and the ground voltage; a firstconnection node, between the first P channel MOS transistor and thefirst N channel MOS transistor, connected to a gate of the second Pchannel MOS transistor; and a second connection node, between the secondP channel MOS transistor and the second N channel MOS transistor,connected to a gate of the first P channel MOS transistor; wherein saidoutput signal is to be supplied via the second connection node to thecircuit that is to be driven by the second power supply voltage; thedriving abilities of the first P channel MOS transistor and the second Pchannel MOS transistor are smaller than the driving abilities of thefirst N channel MOS transistor and the second N channel MOS transistor;and the voltage level conversion circuit further comprises: a fifth Pchannel MOS transistor connected between the first connection node andthe second power supply voltage; a sixth P channel MOS transistorconnected between the second connection node and the second power supplyvoltage; a first signal generation circuit for applying a one-shot pulsevoltage for turning on the sixth P channel MOS transistor to a gate ofthe sixth P channel MOS transistor, when an L level logical voltagegenerated at the first connection node is detected; and a second signalgeneration circuit for applying a one-shot pulse voltage for turning onthe fifth P channel MOS transistor to a gate of the fifth P channel MOStransistor, when an L level logical voltage generated at the secondconnection node is detected.
 5. A voltage level conversion circuit asdefined in claim 4 further comprising: a first resistor connectedbetween the first P channel MOS transistor and the first connectionnode; and a second resistor connected between the second P channel MOStransistor and the second connection node.